Hi erik.
What's the timestamp diff between left/right frame?
DepthAI version: 2.22.0.0
DepthAI path: /home/hiep/anaconda3/envs/depthai/lib/python3.9/site-packages/depthai.cpython-39-x86_64-linux-gnu.so
Connected cameras: ['CAM_A', 'CAM_B', 'CAM_C', 'CAM_D']
-socket CAM_A : IMX477 4056 x 3040 focus:fixed - COLOR
-socket CAM_B : AR0234 1920 x 1200 focus:fixed - COLOR MONO
-socket CAM_C : AR0234 1920 x 1200 focus:fixed - COLOR MONO
-socket CAM_D : AR0234 1920 x 1200 focus:fixed - COLOR MONO
Cam name: {'CAM_A': 'IMX477', 'CAM_B': 'AR0234', 'CAM_C': 'AR0234', 'CAM_D': 'AR0234'}
USB speed: SUPER
left: 0:00:02.132263
right: 0:00:02.132279
camd: 0:00:02.142987
left: 0:00:02.198767
right: 0:00:02.198782
camd: 0:00:02.209492
left: 0:00:02.298522
right: 0:00:02.298536
camd: 0:00:02.309247
left: 0:00:03.861366
right: 0:00:03.861381
camd: 0:00:03.83883
We could see that left/right were software-synced in sub-ms but not the camd ?!?!
Do you trigger HW sync via GPIOs?
No, we haven't triggered HW sync via GPIOS yet. We followed your example but we haven't succeeded to sync the camd to left/right pair and the cameras seemed to freeze (waiting for the triggering pulses I guess). Note that I manually wired the FSIN2&FSIN3 with FSIN1&FSIN4 together instead of configuring the FSIN_MODE_SELECT pin in software.
Update : I realized that your example was for generating a 1ms pulse on IO41 (FSIN_4LANE=FSIN1&FSIN4) which was connected to IO13 (COM_AUX_IO2 = FSIN2&FSIN3). I doubt that IO13 held the pulse to always LOW. If it is the case, how should I configure it correctly or modify the hardware by removing some resistor ?
There seems to be an on-going ticket about the sync of AR0234 on OAK FFC 4P here : luxonis/depthai-python883